They have the same high speed performance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 3 stages including buffer output, which offers high noise immunity and stable output. These devices incorporate a synchronous counter, four-bit D-type register, and quadruple two-line to one-line multiplexers with three-state outputs in a single 20-pin package. The counter can be programmed from the data inputs and have enable P and enable T inputs and a ripplecarry output for easy expansion. The register/counter select input, R/C, selects the counter when low or the register when high for the threestate outputs, QA, QB, QC, and QD. If the LOAD input (LOAD) is held "L" DATA input (AD) are loaded in to the internal counter at positive edge of counter clock input (CCK). In the counter mode, internal counter counts up at the positive of the counter clock. If the counter clear input (CCLR) is held "L", the internal counter is cleared ( synchronously to the counter clock for HC692/HC693, and asynchronously for HC690/HC691). The internal March 1993