These devices have four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA). Each mode is chosen by two function select inputs (S0, S1) as shown in the Truth Table. When one or both enable inputs, (G1, G2) are high, the eight input/output terminals are in the high-impedance state ; however sequential operation or clearing of the register is not affected. Clear function is synchronous to clock. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels.