The SST49LF016C flash memory device is designed to interface with host controllers (chipsets) that support a lowpin-count (LPC) interface for system firmware applications. The SST49LF016C device complies with Intel's LPC Interface Specification 1.1, supporting a Burst-Read (up to 128 bytes in a single operation) which enables a 15.6 MByte per second data transfer. The LPC interface operates with 5 signal pins versus 28 pins of a 8-bit parallel flash memory. This frees up pins on the ASIC host controller resulting in lower ASIC costs and a reduction in overall system costs due to simplified signal routing. The SST49LF016C uses a 5-signal LPC interface to support both in-system and rapid factory programming using programmer equipment. A high voltage pin (WP#/AAI) is used to enable Auto Address Increment (AAI) mode. The 2006 Silicon Storage Technology, Inc. S71237-06-000