The SST45VFxxx uses bus cycles of 8 bits each for commands, data, and addresses to execute operations. The operation instructions are listed in Table 2. All instructions are synchronized off a high to low transition of CE#. The first low to high transition on SCK will initiate the instruction sequence. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. Any low to high transition on CE# before the input instruction completes will terminate any instruction in progress and return the device to the standby mode.