The CXK79M72C165GB (organized as 262,144 words by 72 bits) and the CXK79M36C165GB (organized as 524,288 words by 36 bits) are high speed CMOS synchronous static RAMs with common I/O pins. They are manufactured in compliance with the JEDEC-standard 209 pin BGA package pinouts defined for SigmaRAMTM devices. They integrate input registers, high speed RAM, output registers, and a two-deep write buffer onto a single monolithic IC. Single Data Rate (SDR) Pipelined (PL) read operations and Double Late Write (DLW) write operations are supported, providing a high-performance user interface. Positive and negative output clocks are provided for applications requiring source-synchronous operation. All address and control input signals are registered on the rising edge of the CK input clock. During read operations, output data is driven valid once, from the rising edge of CK, one full cycle after the address and control signals are registered.