The CXK79M36C162GB is a high speed CMOS synchronous static RAM with common I/O pins. It is manufactured in compliance with the JEDEC-standard 209 pin BGA package pinout defined for SigmaRAMTM devices. It integrates input registers, high speed RAM, output registers, and a two-deep write buffer onto a single monolithic IC. Double Data Rate (DDR) Pipelined (PL) read operations and Late Write (LW) write operations are supported, providing a high-performance user interface. Positive and negative output clocks are provided for applications requiring source-synchronous operation. All address and control input signals are registered on the rising edge of the CK differential input clock. During read operations, output data is driven valid twice, from both the rising and falling edges of CK, beginning one full cycle after the address and control signals are registered. During write operations, input data is registered twice, on both the rising and falling edges of CK, beginning one full cycle after the address and control signals are registered. Because two pieces of data are always transferred during read and write operations, the least significant address bit of the internal memory array is not available as an external address pin to this device. Consequently, the number of external address pins available to the device is one less than the specified depth of the device (i.e. the 512Kb x 36 device has 18, not 19, external address pins). And, the user cannot choose the order in which the two pieces of data are read. Read data is always provided in the same order in which it is written. Output drivers are series-terminated, and output impedance is programmable via the ZQ control pin. When an external resistor RQ is connected between ZQ and VSS, the impedance of the SRAM's output drivers is set to ~RQ/5. 300 MHz operation (600 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.