There are no phase-sequence tables, high-frequency control lines, or complex interfaces to program. The CMOS logic section provides the sequencing logic, direction, control, synchronous/asynchronous PWM operation, and a "sleep" function. The minimum CLOCK input is an ideal fit for applications where a complex P is unavailable or overburdened. TTL or LSTTL may require the use of appropriate pull-up resistors to ensure a proper input-logic high. For PWM current control, the maximum output current is determined by the user's selection of a reference voltage and sensing resistor. The NMOS outputs are capable of sinking up to 1, 1.5, 2, or 3 A (depending on device) and withstanding 46 V in the off state. Clamp diodes provide protection against inductive transients. Special power-up sequencing is not required. Full-,and Half-step operation are externally selectable for the SLA7070/71/72/73MR. Full-, Half-, quarter-, and eighth-, and sixteenth-step operation are externally selectable for the SLA7075/76/77/78MR.