The device may also be triggered by using the CLR input (positiveedge) because of the Schmitt-trigger input; after triggering the output maintains the MONOSTABLE state for the time period determined by the external resistor RX and capacitor CX. Taking CLR low breaks this MONOSTABLE STATE. If the next trigger pulse occurs during the MONOSTABLE period it makes the MONOSTABLE period longer. Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 3.0 to 6.0 V Low Input Current: 1.0 A