The Si5311 is a fully integrated high-speed clock multiplier and clock regenerator IC. The clock multiplier generates an output clock that is an integer multiple of the input clock. When the clock multiplier is operating in either the 150167 MHz range or the 600668 MHz range, the clock regenerator operates simultaneously. The clock regenerator creates a "clean" version of the input clock by using the clock synthesis phaselocked loop (PLL) to remove unwanted jitter and square up the input clock's rising and falling edges. The Si5311 uses Silicon Laboratories patented DSPLLTM architecture to achieve superior jitter performance while eliminating the analog loop filter found in traditional PLL designs.