The Si5100 is a complete low-power transceiver for high-speed serial communication systems operating between 2.5 Gbps and 2.7 Gbps. The receive path consists of a fully integrated limiting amplifier, clock and data recovery unit (CDR), and 1:16 deserializer. The transmit path combines a low jitter clock multiplier unit (CMU) with a 16:1 serializer. The CMU uses Silicon Laboratories' DSPLLTM technology to provide superior jitter performance while reducing design complexity by eliminating external loop filter components. To simplify BER optimization in long haul applications, programmable slicing and sample phase adjustment are supported.