The Si5310 is a fully integrated low-power clock multiplier and clock regenerator IC. The clock multiplier generates an output clock that is an integer multiple of the input clock. The clock regenerator operates simultaneously, creating a "clean" version of the input clock by using the clock synthesis phase-locked loop (PLL) to remove unwanted jitter and square up the input clock's rising and falling edges. The Si5310 uses Silicon Laboratories patented DSPLL architecture to achieve superior jitter performance while eliminating the analog loop filter found in traditional PLL designs with a digital signal-processing algorithm.