The Si5017 is a fully-integrated, high-performance limiting amplifier (LA) and clock and data recovery (CDR) IC for high-speed serial communication systems. It derives timing information and data from a serial input at OC-48 and STM-16 rates. Support for 2.7 Gbps data streams is also provided for OC-48/STM-16 applications that employ forward error correction (FEC). Use of an external reference clock is optional. Silicon Laboratories DSPLL technology eliminates sensitive noise entry points, thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance.