The Driver circuit is capable of forcing two levels to the DUT (DVH and DVL) as well as a third voltage for a termination level (DVT) to terminate high-speed DUT signals to the Comparator receivers into a high quality 50 load. The Driver can also be configured to a high impedance (HiZ) state for an open termination of DUT signals. Waveform clamps are also available to clip the input signals from a DUT when not using the Driver as a termination. The clamps prevent reflections from returning to the DUT transmission line which can create timing errors and false triggering.