The SA2030 is designed to interface PCM-30 routes with switching systems. The device synchronises with the frame-format of the incoming data, and outputs this data in accordance with the bit and frame timing of the terminating equipment. The circuit is designed to tolerate delay, drift, wander and jitter of the incoming data and clock, and thus simplifies the design of data- and clock-recovery hardware. The internal 1 frames elastic buffer provides for delay compensation and wander immunity. If the bounds of the buffer are exceeded, the SA2030 will either repeat or drop a frame. The circuit will accurately detect incoming Alarm-Indication-Signal (AIS) conditions, in accordance with CCITT recommendation G.737. Loss of frame alignment is indicated on both dedicated outputs and by outputting of AIS. The circuit includes a bidirectional alarm port for interrogation of alarm conditions. M74-1885