The part is generally operated to conform to ACPI specification, in S3 state, there are only VDDQ and 3.3VSB regulators remain on while the VTT and ULDO regulators are off. In the transition from S3 to S0, an external SS capacitor is attached for linear regulators to control its slew rates respectively to avoid inrush current induced. Moreover, the PGOOD signal raises high in S0 stage while all 3 regulators go stable. In the stage of S5 (EN = 0), there only 3.3VSB LDO remain on, while the other regulators are powered down. The VDDQ PWM regulator is a voltage mode implementation with external compensation to provide high load transient response. The VTT is regulated to follow 1/2 of VDDQ and is capable of sourcing or sinking 1.5A peak currents.