|
|
Partname: | HD74SSTV16857ATEL |
Description: | 1:1 14-bit SSTL_2 Registered Buffer |
Manufacturer: | |
Datasheet: | PDF (215K). Click here to download *) |
The HD74SSTV16857A is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input. Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise margins. When RESET is low, all registers are reset and all outputs are low. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. |
|
Click here to download HD74SSTV16857ATEL Datasheet*) |
|
*)Datasheets downloading from ChipDocs is only for our members (paid service). REGISTER NOW for your membership. |
|
|
|