The 18-bit PI74ALVCH16823 bus-interface flip-flop is designed for 2.3V to 3.6V VCC operation. It features 3-state outputs designed specifically for driving highly capacitive or relatively lowimpedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The PI74ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the Clock Enable (CLKEN) input LOW, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN HIGH disables the clock buffer, thus latching the outputs. Taking the Clear (CLR) input LOW causes the Q outputs to go LOW independently of the clock. A buffered Output Enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.