The 18-bit PI74ALVCH16500 univeral bus transceiver is designed for 2.3V to 3.6V Vcc operation. Data flow in each direction is controlled by Output Enable (OEAB and OEBA), Latch- Enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A- to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the highto-low transition of CLKAB. Output-enable OEAB is active high. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are in the high-impedence state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The Output Enables are complementary (OEAB is active HIGH and OEBA is active LOW). To ensure the high-impedance state during power up or power down, OEBA should be tied to Vcc through a pull-up resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/ current-sourcing capability of the driver.