The PI6C2520 is a low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing low-noise clock signals for Networking Applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. This zero-delay feature allows the CLK_IN input clock to be distributed, providing 5 banks of 4 clocks and an extra clock for feedback.