The PI6C2309-1 provides 9 copies of a clock signal that has less than 200ps propagation delay compared to the reference clock. The skew among the output clock signals for PI6C2309-1 is less than 250ps. When there are no rising edges on the REF input, the PI6C2309-1 enters a power-down state. In this mode, the PLL is off and all outputs are three-stated. This results in less than 50A of current draw.