The GTLP16612A 18-bit universal transceiver provides TTL to GTLP signal level translation. The device is designed to provide highspeed interface between cards operating at TTL logic levels and a back plane operating at GTLP logic levels. High-speed back plane operation is a direct result of GTLPs reduced output swing (<1V), reduced input threshold levels, and output edge-rate control which minimizes signal settling times. Its function is similar to BTL or GTL but with modified driver output levels and receiver threshold. GTLP output low voltage is typically less than 0.5V, the output high is 1.5V, and the receiver threshold is 1.0V.