The PDM34089 is a 2,097,152 bit synchronous random access memory organized as 65,536 x 32 bits. It is designed with burst mode capability and interface controls to provide high-performance in second level cache designs for x86, Pentium, 680x0, and PowerPC microprocessors. Addresses, write data and all control signals except output enable are controlled through positive edge-triggered registers. Write cycles are self-timed and are also initiated by the rising edge of the clock. Controls are provided to allow burst reads and writes of up to four words in length. A 2-bit burst address counter controls the two least-significant bits of the address during burst reads and writes. The burst address counter selectively uses the 2-bit counting scheme required by the x86 and Pentium or 680x0 and PowerPC microprocessors as controlled by the mode pin. Individual write strobes provide byte write for the four 8-bit bytes of data. An asynchronous output enable simplifies interface to high-speed buses.