The NCP5201 Dual DDR Power Controller is specifically designed as a total power solution for a high current DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of a linear regulator for the VTT memory termination voltage. The secondary regulator (VTT) is designed to automatically track at half the primary regulator voltage (VDDQ). An internal power good voltage monitor tracks both VDDQ and VTT outputs and notifies the user in the event of a fault on either output. Protective features include soft-start circuitry and undervoltage monitoring of VCC and VSTBY. The IC is packaged in a 5 x 6 QFN-18.