The Multi-Level Inputs can be driven directly by differential LVPECL, LVDS or CML logic levels; or by single ended LVPECL, LVCMOS or LVTTL. A single enable pin is available to control both inputs. The SDI input pins are controlled by LVCMOS or LVTTL level signals. The NB6L295 LVPECL output contains temperature compensation circuitry. This device is offered in a 4 mm x 4 mm 24-pin QFN Pb-free package. The NB6L295 is a member of the ECLinPS MAXTM family of high performance products. Input Clock Frequency > 1.5 GHz with 550 mV 3 ps Typical Clock Jitter, RMS VOUTPP