The NB100EP223 is a low skew 1-to-22 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are differential HSTL or LVPECL and they are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous ensuring the outputs will only be enabled/disabled when they are already in LOW state (See Figure 7). The NB100EP223 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. In any differential output pair, the same bias and termination scheme is required. Unused output pairs should be left unterminated (open) to "reduce power and switching noise as much as possible." Any unused single line of a differential pair should be terminated the same as the used line to maintain balanced loads on the differential driver outputs. The output structure uses an open emitter architecture and will be terminated with 50 W to ground instead of a standard HSTL configuration (See Figure 6). The wide VIHCMR specification allows both pair of CLOCK inputs to accept LVDS levels.