The MC74AC273/74ACT273 has eight edge-triggered Dtype flipflops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flipflops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOWtoHIGH clock transition, is transferred to the corresponding flipflop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.