The MC14526B binary counter is constructed with MOS Pchannel and Nchannel enhancement mode devices in a monolithic structure. This device is presettable, cascadable, synchronous down counter with a decoded "0" state output for dividebyN applications. In single stage applications the "0" output is applied to the Preset Enable input. The Cascade Feedback input allows cascade dividebyN operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock.