The MC100LVEP210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single-ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be used when the EP210 is operating in PECL mode. The LVEP210 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.