The 8-lead SOIC evaluation board is implemented in four layers with split (dual) power supplies (Figure 2. Evaluation Board Lay-up). For standard ECL lab setup and test, a split (dual) power supply is essential to enable the 50 W internal impedance in the oscilloscope as a termination for ECL devices. The first layer or primary trace layer is 0.008 thick Rogers RO4003 material, which is designed to have equal electrical length on all signal traces from the device under the test (DUT) to the sense output. The second layer is the 1.0 oz copper ground plane and a portion of the plane is the VEE power plane. The FR4 dielectric material is placed between second and third layer and between third and fourth layer. The third layer is also 1.0 oz copper ground plane and a portion of this layer is VCC power plane. The fourth layer is the secondary trace layer.