The attached SPICE Model describes typical electrical characteristics of the pchannel vertical DMOS. The subcircuit model was extracted and optimized over a 25C to 125C temperature range under pulse conditions for 0 to 5 volts gate drives. Saturated output impedance model accuracy has been maximized for gate biases near threshold. A novel gatetodrain feedback capacitor network is used to model gate charge characteristics while avoiding convergence problems of switched Cgd model. Model parameter values are optimized to provide a best fit to measure electrical data and are not intended as an exact physical description of a device.