These CMOS counters consist of a 4-digit counter an internal output latch NPN output sourcing drivers for a 7-segment display and an internal multiplexing circuitry with four multiplexing outputs The multiplexing circuit has its own free-running oscillator and requires no external clock The counters advance on negative edge of clock A high signal on the Reset input will reset the counter to zero and reset the carry-out low A low signal on the Latch Enable input will latch the number in the counters into the internal output latches A high signal on Display Select input will select the number in the counter to be displayed a low level signal on the Display Select will select the number in the output latch to be displayed