These high speed OCTAL D-TYPE LATCHES utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power consumption of standard CMOS integrated circuits as well as the ability to drive 15 LS-TTL loads Due to the large output drive capability and the TRI-STATE feature these devices are ideally suited for interfacing with bus lines in a bus organized system When the LATCH ENABLE input is high the data present on the D inputs will appear inverted at the Q outputs When the LATCH ENABLE goes low the inverted data will be retained at the Q outputs until LATCH ENABLE returns high again When a high logic level is applied to the OUTPUT CONTROL input all outputs go to a high impedance state regardless of what signals are present at the other inputs and the state of the storage elements