These devices utilize advanced silicon-gate CMOS technology to implement a three-to-eight line decoder with latches on the three address inputs When GL goes from low to high the address present at the select inputs (A B and C) is stored in the latches As long as GL remains high no address changes will be recognized Output enable controls G1 and G2 control the state of the outputs independently of the select or latch-enable inputs All of the outputs are low unless G1 is high and G2 is low The 'HC237 is ideally suited for the implementation of glitch-free decoders in storedaddress applications in bus oriented systems