The input accepts standard analog SD/ED/HD video signals with either bi-level or tri-level sync, and the outputs provide all of the critical timing signals in CMOS logic, which swing from rail-to-rail (VCC and GND) including Composite, Horizontal, and Vertical Syncs, Burst/Back Porch Timing, Odd/ Even Field, and Video Format Outputs. HSync features very low jitter on its leading (falling) edge, minimizing external circuitry needed to clean and reduce jitter in subsequent clock generation stages.