The maximum PWM duty cycle is limited to less than 75% to reduce voltage stress on the power MOSFETs. The CS2 hiccup mode threshold is increased to 0.5V The CS2 filter discharge device is disabled The VCC regulator continues to operate when the line UVLO is below the threshold of normal operation The VREF regulator is switched off when the line UVLO input falls below the operating threshold The internal 5k COMP pin pull-up resistor is removed The LM5025B PWM controller contains all of the features necessary to implement power converters utilizing the Active Clamp / Reset technique. With the active clamp technique, higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp / reset techniques. Two control outputs are provided, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The two internal compound gate drivers parallel both MOS and Bipolar devices, providing superior gate drive characteristics. This controller is designed for high-speed operation including an oscillator frequency range up to 1MHz and total PWM and current sense propagation delays less than 100ns.