The DS90CF581 transmitter converts 28 bits of CMOS TTL data into four LVDS (Low Voltage Differential Signaling) data streams A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link Every cycle of the transmit clock 28 bits of input data are sampled and transmitted The DS90CF582 receiver converts the LVDS data streams back into 28 bits of CMOS TTL data At a transmit clock frequency of 40 MHz 24 bits of RGB data and 4 bits of LCD timing and control data (FPLINE FPFRAME DRDY CNTL) are transmitted at a rate of 280 Mbps per LVDS data channel Using a 40 MHz clock the data throughput is 140 Megabytes per second The chipset is an ideal means to solve EMI and cable size problems associated with wide high speed TTL interfaces