The DS8906 is a PLL synthesizer designed specifically for use in AM FM radios It contains the reference oscillator a phase comparator a charge pump a 120 MHz ECL I2L dual modulus programmable divider and a 20-bit shift register latch for serial data entry The device is designed to operate with a serial data controller generating the necessary division codes for each frequency and logic state information for radio function inputs outputs The Colpitts reference oscillator for the PLL operates at 4 MHz A chain of dividers is used to generate a 500 kHz clock signal for the external controller Additional dividers generate a 12 5 kHz reference signal for FM and a 500 Hz reference signal for AM SW One of these reference signals is selected by the data from the controller for use by the phase comparator Additional dividers are used to generate a 50 Hz timing signal used by the controller for ``time-ofday'' Data is transferred between the frequency synthesizer and the controller via a 3 wire bus system This consists of a data input line an enable line and a clock line When the enable line is low data can be shifted from the controller into the frequency synthesizer When the enable line is transitioned from low to high data entry is disabled and data present in the shift register is latched From the controller 22-bit data stream the first 2 bits address the device permitting other devices to share the same bus Of the remaining 20-bit data word the next 14-bits are used for the PLL divide code The remaining 6 bits are connected via latches to output pins These 6 bits can be used to drive radio functions such as gain mute FM AM LW and SW only These outputs are open collector Bit 18 is used internally to select the AM or FM local oscillator input and to select between the 500 Hz and 12 5 kHz reference A high level at bit 18 indicates FM and a low level indicates AM The PLL consists of a 14-bit programmable I2L divider an ECL phase comparator an ECL dual modulus (p p a 1) prescaler and a high speed charge pump The programmable divider divides by (N a 1) N being the number loaded into the shift register (bits 114 after address) It is clocked by the AM input via an ECL d 7 8 prescaler or through a d 63 64 prescaler from the FM input The AM input will work at frequencies up to 8 MHz while the FM input works up to 120 MHz The AM band is tuned with a frequency resolution of 500 Hz and the FM band is tuned with a resolution of 12 5 kHz The buffered AM and FM inputs are self-biased and can be driven directly by the VCO thru a capacitor The ECL phase comparator produces very accurate resolution of the phase difference between the input signal and the reference oscillator