The DS8838 is a quad high speed driver/receiver designed for use in bus organized data transmission systems interconnected by terminated 120 impedance lines. The external termination is intended to be 180 resistor from the bus to the +5V logic supply together with a 390 resistor from the bus to ground. The bus can be terminated at one or both ends. Low bus pin current allows up to 27 driver/receiver pairs to utilize a common bus. The bus loading is unchanged when VCC = 0V. The receivers incorporate hysteresis to greatly enhance bus noise immunity. One two-input NOR gate is included to disable all drivers in a package simultaneously. Receiver performance is optimized for systems with bus rise and fall times 1.0 s/V.