The DS3883A is one in a series of transceivers designed specifically for the implementation of high performance Futurebus+ and proprietary bus interfaces. The DS3883A, is a BTL 9-bit Transceiver designed to conform to IEEE 1194.1 (Backplane Transceiver Logic -- BTL) as specified in the IEEE 896.2 Futurebus+ specification. Utilization of the DS3883A simplifies the implementation of byte wide address/data with parity lines and also may be used for the Futurebus+ status, tag and command lines. The DS3883A driver output configuration is an NPN open collector which allows Wired-OR connection on the bus. Each driver output incorporates a Schottky diode in series with its collector to isolate the transistor output capacitance from the bus thus reducing the bus loading in the inactive state. The combined output capacitance of the driver and receiver input is less than 5 pF. The driver also has high sink current capability to comply with the bus loading requirements defined within IEEE 1194.1 BTL specification. Backplane Transceiver Logic (BTL) is a signaling standard that was invented and first introduced by National Semiconductor, then developed by the IEEE to enhance the performance of backplane buses. BTL compatible transceivers feature low output capacitance drivers to minimize bus loading, a 1V nominal signal swing for reduced power consumption and receivers with precision thresholds for maximum noise immunity. BTL eliminates settling time delays that severely limit TTL bus performance, and thus provide significantly higher bus transfer rates. The backplane bus is intended to be operated with termination resistors (selected to match the bus impedance) connected to 2.1V at both ends. The low voltage is typically 1V. Separate ground pins are provided for each BTL output to minimize induced ground noise during simultaneous switching.The unique driver circuitry meets the maximum slew rate of 0.5 V/ns which allows controlled rise and fall times to reduce noise coupling to adjacent lines.The transceiver's control and driver inputs are designed with high impedance PNP input structures and are fully TTL compatible. The receiver is a high speed comparator that utilizes a bandgap reference for precision threshold control allowing maximum noise immunity to the BTL 1V signaling level. Separate QVCC and QGND pins are provided to minimize the effects of high current switching noise. The output is TRI-STATE and fully TTL compatible.