The DP8520A 21A 22A video RAM controllers provide a low cost single chip interface between video RAM and all 8- 16- and 32-bit systems The DP8520A 21A 22A generate all the required access control signal timing for VRAMs An on-chip refresh request clock is used to automatically refresh the VRAM array Refreshes and accesses are arbitrated on chip If necessary a WAIT or DTACK output inserts wait states into system access cycles including burst mode accesses RAS low time during refreshes and RAS precharge time after refreshes and back to back accesses are guaranteed through the insertion of wait states Separate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back accesses because of precharge An additional feature of the DP8522A is two access ports to simplify dual accessing Arbitration among these ports and refresh is done on chip