The DP8402A DP8403 DP8404 and DP8405 devices are 32-bit parallel error detection and correction circuits (EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404 and DP8405 600-mil packages The EDACs use a modified Hamming code to generate a 7-bit check word from a 32-bit data word This check word is stored along with the data word during the memory write cycle During the memory read cycle the 39-bit words from memory are processed by the EDACs to determine if errors have occurred in memory Single-bit errors in the 32-bit data word are flagged and corrected Single-bit errors in the 7-bit check word are flagged and the CPU sends the EDAC through the correction cycle even though the 32-bit data word is not in error The correction cycle will simply pass along the original 32-bit data word in this case and produce error syndrome bits to pinpoint the error-generating location