The BCP integrates a 20 MHz 8-bit Harvard architecture RISC processor and an intelligent software-configurable transceiver on the same low power microCMOS chip The transceiver is capable of operating without significant processor interaction releasing processor power for other tasks Fast and flexible interrupt and subroutine capabilities with on-chip stacks make this power readily available The transceiver is mapped into the processor's register space communicating with the processor via an asynchronous interface which enables both sections of the chip to run from different clock sources The transmitter and receiver run at the same basic clock frequency although the receiver extracts a clock from the incoming data stream to ensure timing accuracy