The DP83222 CYCLONE Stream Cipher Scrambler Descrambler Device is an integrated circuit designed to interface directly with the serial bit streams of a Twisted Pair FDDI PMD The DP83222 is designed to be fully compatible with the National Semiconductor FDDI Chip Sets including the DP83223 TWISTERTM (Twisted Pair Transceiver) The DP83222 requires a 125 MHz Transmit Clock and corresponding Receive Clock for synchronous data scrambling and descrambling The DP83222 is compliant with the ANSI X3T9 5 TP-PMD draft standard and is required for the reduction of EMI emission over unshielded media The DP83222 is specified to work in conjunction with existing twisted pair transceiver signalling schemes such as MLT-3 or NRZI and enables high bandwidth transmission over Twisted Pair copper media