The '122 features positive and negative DC level triggering inputs complementary outputs an optional 10 kX internal timing resistor and an overriding Direct Clear (CD) input When the circuit is in the quasi-stable (delay) state another trigger applied to the inputs (per Truth Table) will cause the delay period to start again without disturbing the outputs This process can be repeated indefinitely and thus the output pulse period (Q HIGH Q LOW) can be made as long as desired Alternatively a delay period can be terminated