The CD4031BM CD4031BC is an integrated complementary MOS (CMOS) 64-stage fully static shift register Two data inputs DATA IN and RECIRCULATE IN and a MODE CONTROL input are provided Data at the DATA input (when MODE CONTROL is low) or data at the RECIRCULATE input (when MODE CONTROL is high) which meets the setup and hold time requirements is entered into the first stage of the register and is shifted one stage at each positive transition of the CLOCK Data output is available in both true and complement forms from the 64th stage Both the DATA OUT (Q) AND DATA OUT (Q) outputs are fully buffered The CLOCK input of the CD4031BM CD4031BC is fully buffered and present only a standard input load capacitance However a DELAYED CLOCK OUTPUT (CLD) has been provided to allow reduced clock drive fan-out and transition time requirements when cascading packages