These (synchronous presettable up) counters are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors They feature an internal carry look-ahead for fast counting schemes and for cascading packages without additional gating A low level at the load input disables counting and causes the outputs to agree with the data input after the next positive clock edge The clear function for the CD40162B and CD40163B is synchronous and a low level at the clear input sets all four outputs low after the next positive clock edge The clear function for the CD40160B and CD40161B is asynchronous and a low level at the clear input sets all four outputs low regardless of the state of the clock Counting is enabled when both count enable inputs are high Input T is fed forward to also enable the carry out The carry output is a positive pulse with a duration approximately equal to the positive portion of QA and can be used to enable successive cascaded stages Logic transitions at the enable P or T inputs can occur when the clock is high or low