The ADC12DS065, ADC12DS080, ADC12DS095, and ADC12DS105 are high-performance CMOS analog-to-digital converters capable of converting two analog input signals into 12-bit digital words at rates up to 65/80/95/105 Mega Samples Per Second (MSPS) respectively. The digital outputs are serialized and provided on differential LVDS signal pairs. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12DS065/080/095/105 may be operated from a single +3.3V power supply and consumes low power. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs provide a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC12DS065/080/095/105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles. The ADC12DS065/080/095/105 is available in a 60-lead LLP package and operates over the industrial temperature range of -40C to +85C.