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Partname:54LS113
Description:Dual JK Edge-Triggered Flip-Flop
Manufacturer:National Semiconductor
Datasheet:PDF (98.0K).
Click here to download *)

The 54LS113 offers individual J K Set and Clock inputs When the clock goes HIGH the inputs are enabled and data may be entered The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed Input data is transferred to the outputs on the falling edge of the clock pulse

Click here to download 54LS113 Datasheet
Click here to download 54LS113 Datasheet
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