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| Partname: | SN74LS109AD |
| Description: | Dual JK negative edge-triggered flip-flop |
| Manufacturer: | Motorola |
| Package: | SOIC |
| Pins: | 16 |
| Oper. temp.: | 0 to 70 |
| Datasheet: | PDF (147K).
Click here to download *) |
The SN54/ 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. |
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Click here to download SN74LS109AD Datasheet*) |
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