The MPC7450 is the third implementation of the fourth generation (G4) microprocessors from Motorola. The MPC7450 implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The MPC7450 consists of a processor core, a 256-Kbyte L2, and an internal L3 tag and controller which support a glueless backside L3 cache through a dedicated high bandwidth interface. Figure 1 shows a block diagram of the MPC7450. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus interface to main memory and other system resources. The L3 interface supports 1 or 2 Mbytes of external SRAM for L3 cache data.